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Espressif Systems /ESP32-S3 /ASSIST_DEBUG /CORE_1_DRAM0_EXCEPTION_MONITOR_0

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Interpret as CORE_1_DRAM0_EXCEPTION_MONITOR_0

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31282724232019161512118743000000000000000000000000000000000000000000CORE_1_DRAM0_RECORDING_ADDR_00 (CORE_1_DRAM0_RECORDING_WR_0)CORE_1_DRAM0_RECORDING_WR_0

Description

Core1 bus busy status regsiter

Fields

CORE_1_DRAM0_RECORDING_ADDR_0

The first dram0’s addr[25:4] status when trigger DRAM busy interrupt
CORE_1_DRAM0_RECORDING_WR_0

The first dram0’s wr status when trigger DRAM busy interrupt

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data